1. Field of the Invention
This invention is related to joining semiconductor substrates. More specifically, the present invention provides a high density interconnect structure and method for joining or coupling together substrates employing deformable bonding sheet.
2. Description of the Prior Art
A patentability investigation was conducted and the following U.S. Patents were discovered: U.S. Pat. No. 5,376,403 to Capote et al.; U.S. Pat. No. 5,128,746 to Pennisi et al.; U.S. Pat. No. 5,232,532 to Hori; U.S. Pat. No. 5,157,828 to Coques et al.; U.S. Pat. No. 5,187,123 to Yoshida et al.; U.S. Pat. No. 5,839,188 to Pommer; and U.S. Pat. No. 5,842,273 to Schor.
U.S. Patent No. 5,376,403 to Capote et al. discloses electrically conductive compositions which contain metal and solder in addition to polymer forming constituents. A technique is described for eliminating voids in bonding a chip to a flexible substrate. A flexible pad or paper is connected to the underside of the flexible substrate, which will deform during bonding and allow air to flow out of the liquid adhesive before it cures and hardens. The adhesive used to bond the chip to the flexible substrate is liquid or paste (not bonding film or sheet) and the objective is air bubble elimination during bonding.
U.S. Pat. No. 5,128,746 to Pennisi et al. teaches a flux containing polymer forming composition. The flux forming constituent is disclosed as an acid selected from the group consisting of abietic acid, adipic acid, ascorbic acid acrylic and, citric acid, and malic acid.
U.S. Pat. No. 5,232,532 to Hori describes a technique for eliminating voids in bonding of a chip to a flexible substrate. The goal is to use flexible pad or paper underneath the flexible substrate, which will deform during bonding and allow air to flow out of the liquid adhesive before it cures and hardens.
U.S. Pat. No. 5,127,828 to Coques et al. describes use of an adhesive loop between a substrate and a support so that a partial vacuum may be applied to the space between the substrate and the support. The objective is to have uniform squeezing of adhesive and therefore uniform spacing between the substrate and the support after the adhesive is cured.
U.S. Pat. No. 5,187,123 to Yoshida et al. describes a void free adhesive layer in bonding of a semiconductor device to a lead frame. The main area of adhesive application is the back side of the die. There is no metal connection between the semiconductor device and the lead frame. The adhesive is applied in liquid or paste form in several pre-arranged spots, so as to prevent formation of voids during semiconductor device attachment onto a lead frame.
U.S. Pat. No. 5,839,188 to Pommer discloses the use of non-conductive particles (i.e., “gauge” particles) to provide a uniform gap or separation between two or more substrates, and the use of conductive pastes of copper post/tin to form an electrical interconnection.
U.S. Pat. No. 5,842,273 to Schor discloses the use of a conductive adhesive to from an electrical connection between substrates. The adhesive is an elastomeric thermoset with conductive particles, flakes, etc. No solder is used. Electrical connection is primarily through metal contact.
Conventional underfill process, such as that disclosed in the foregoing prior art, for flip chip to substrate joining is limited to very small joining areas (typically 1-inch by 1-inch area or less). Substrate buildup is expensive. As the requirements of high density substrates increase, a simple and reliable interconnection process is needed to fulfill this demand. For typical solder printing methods, there is a limitation on the size of solder bumps, and the yield will be low for fine-pitch small bumps. Furthermore, joints will be less reliable on micro-bumps. It is desirable to have an interconnect reliable process that may be easily down-sized to the dimension of HDI substrates. Therefore, what is needed and what has been invented is an economical method that can provide the foregoing requirements by employing an insertion structure and a transient liquid alloy bonding.